Monday, 22 December 2014

CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN( 2 marks with answers)



CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN

2 Marks with Answers

UNIT-I

 BOOLEAN ALGEBRA AND LOGIC GATES



1.  Define Digital system.
               A digital system is a system that manipulates discrete elements of information that is represented internally in binary form.

2.  Convert (98)10 to Binary?
Number                     Divide by                   Remainder
98                2                           0
49                2                           1
24                2                           0                 
12                2                           0       
6                  2                           0
3                  2                           1
1                 
(98)10 = (1100010)2

3.  Convert (67)8 to Decimal? (67)8
                   7*80=7
                        6*81=48
                             (67)8=(55)10        

4.  Convert (101111100)2 to Octal?
(101 111 100)2
101-5
111-7
100-4
          (101 111 100)2= (574)8
                  
5.  Convert (1110111100.10110001)2 to Hexadecimal?
               (0011 1011 1100 . 1011 0001)2= (3BC.B1)16

6.  Convert (0.513)10 to Octal?
0.513 * 8 = 4.104
0.104 * 8 = 0.832
0.832 * 8 = 6.656
0.656 * 8 = 5.248
(0.513)10 = (0.4065)8

7.  If X=1010100 and Y=1000011, perform subtraction using 2’s complement?
                             X        1010100
                             Y        0111101
                                      -----------
                                 1   0010001       
              Discard end carry, answer=      0010001       

8.  Convert (3872)10 to i.) BCD and ii.) Gray Code?
i.)     (3872)10 =(0011 1000 0111 0010)2
ii.)    (3872)10 =(0010 1100 0100 0011)2

9.  Write Excess-3 code and 2421 for (1902)10 ?
               Excess-3 Code:
               (1902)10=(0100 1100 0011 0101)2
               2421:
               (1902)10=(0001 1111 0000 0010)2
                       (0001 1111 0000 1000)2

10. Write Associative law and Commutative Law for i.) (X*Y)*Z       ii.) X*(Y.Z)
                   i.) (X*Y)*Z     = X*(Y*Z)
                   ii.) X*(Y.Z)     = (X*Y). (X*Z)

11. Differentiate negative and positive logic? [AU Dec. 2009]
               In positive logic, 1 is high                       0 is low
               In negative logic, 1 is low                       0 is high

12. What are Canonical forms and standard forms?
                       A Boolean function can be expressed either as sum of minterms or product of maxterms which are known as canonical forms, where minterms are possible combinations of given inputs of an application using AND operation and maxterms are possible combinations of given inputs of an application using OR operation.
                   Standard form is one of the ways to express a Boolean function, which can be given by sum of products or Product of sums.         The sum of products is a Boolean expression consists of a group of AND terms, called product terms, of one or more literals each and the sum denotes OR operation. The product of sums is a Boolean expression containing OR terms, called sum terms and the product denotes ANDing of these terms.
13. Simplify the Boolean Function F(X, Y, Z) =?
               00  01 10  11

1
1
1
1


                                      F = X1Y + XY1

14. Give the Expressions and truth tables for half adder [AU Nov/Dec 2014]
               Half adder:     Sum       =x’y+xy’
                             Carry  =xy
              
X
Y
Carry
Sum
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0


15. What are minterms and maxterms? [AU Dec 2009]
               Minterm:
These are possible combinations of given inputs of an application using AND operation by which the function will be given as sum of minterms.
               Maxterm: [AU April / May 2011]
These are possible combinations of given inputs of an application using OR operation by which the function will be given as product  of maxterms.

16. How the functions are represented and conversions are achieved?
                             The functions can be expressed in either sum of minterms or product of maxterms.                  F(X,Y,Z)= ∑(2,3,4,5)=∏(0,1,6,7)    
    
17. What is the general procedure to convert multilevel And-OR to all all-NAND diagram?
               Procedure is given as follows:
                   1.Convert all AND gates to NAND with invert AND graphic symbol.
                   2. Convert all OR gates to NOR with invert OR graphic symbol.
                   3.Check the bubbles of the diagram.
              
18. Give example for self-complementing code and weighted code.
                   2421 and excess-3 code are examples of self complementing code.
                   BCD(8421) and 2421 are weighted code.

19. What is binary cell?
          A binary cell is a device that possesses two stable states and is capable of storing one bit of information.

20. What is register?
          Register is a group of binary cells.

21. Define Binary Logic.
                   Binary Logic consists of binary variables and logical operations. The variables are designated by alphabet such as A,B,C,x,y,z with each variable having two possible values 0 and 1.Logical operations are AND,OR,NOT.

22. What are the levels of  integration?
·                     Small-scale integration (SSI)
·                     Medium-scale integration (MSI)
·                     Large-scale integration(LSI)
·                     Very large-scale integration(VLSI)
         
23. Give some examples of Digital Logic families.
·                     TTL-  Transistor-transistor Logic
·                     ECL- Emitter-Coupled Logic
·                     MOS- Metal-oxide semiconductor
·                     CMOS- Complementary metal-oxide semiconductor.

24. Define Fan-in and Fan-out.
          Fan-in: It is the number of inputs available in a gate.
          Fan-out: specifies the number of standard loads that the output of a typical gate can drive without impairing its normal operation.

25. Define Propagation delay.
          It is the average transition delay time for the signal to propagate from input to output.

26. What is meant by weighted and Non Weighted Codes?
            Weighted binary codes obey their positional weighting principle. Each Bit has position weight.
          Example: 8421, 2421.
                      Non weighted binary codes are not positional weighted.
          Example: Excess 3 code, Gray Code. [AU Nov / Dec 2011]

27. What is an ASCII code?
                        ASCII stands for American Standard for Information Interchange. These are used to represent the characters in binary form. ASCII is a seven bit code. The first three bits are standard 100 and other 4 bits changes according to the character. For example, 100 0001 represents character A.

28. What is an Excess 3 code?
                   The name excess 3 code itself implies, it gives the excess 3 of the given decimal number in binary form. An excess 3 code can be obtained by adding 3 with the original number. An excess 3 code is a self complement code. Most of the application of this will be in subtraction operation in digital computers.

29. What is Cyclic Redundancy Check?
                        The CRC is a bit checking method used to detect the data error when transmitted through the network. The transmitted and received bits are cross checked.

30. What is SOP and POS? Give the standard representation for the same.
                        SOP: The logical sum of the several product variables is called Sum Of Product. It is basically an OR operation of AND operated variables.
                                      Y = AB+BC+CA
                   POS: The logical product of the several sum variables is called Product Of Sum. It is basically an OR operation of AND operated variables.
                                      Y = (A+B)(B+C)(C+A)

31. State DeMorgan’s theorem. [AU Nov / Dec 2010]
                        The first theorem states that the complement of a product is equal to the sum of the complements.
                                                (AB)’ = A’+ B’
                   The second theorem states that the complement of a sum is equal to the product of the complements.
                                                (A+B)’ = A’. B’

32. Define Principle of Duality. [AU Dec 2009]
                        Principle of duality states that, the result of any expression can be obtained same if the bit (0 or 1) and operator AND and OR is replaced.
                             Example:  A (B+1) = A
                                           A + (B.0) = A

33. What are don’t care conditions?
                        In some logic circuits certain input conditions never occur, therefore the corresponding output never appears. In such cases the output level is not defined, it can be either high or low. These output levels are indicated by X or d in the truth tables and are called don’t care conditions or incompletely specified functions.

34. Compare K- map and Quine – McKluskey method for realizing a function?

K - Map
Quine – McKluskey
Up to 4 variable functions, K-Map is short method.
This method is efficient for more than 4 variables.
Redundant terms cannot be eliminated.
Redundant terms can be eliminated easily.






35. What are disadvantages of k –map?
                   a) For more than 4 input variables, k-map is complex to solve.
                   b) Redundant terms cannot be eliminated.

36. Realize OR gate using only NAND gates. [AU Nov / Dec 2012]
 


37. Write the application of gray code. [AU May /June 2012]
                        Used in application where the normal sequence of binary numbers may produce an error or ambiguity during the transition from one number to the next.

38. The roots of the quadratic equation x^2-12x+37=0 are 5 and 8. Find the base system in which this equation is written?
            If the roots are 5 and 8, then the equation can be written as
%28x-5%29%28x-8%29+=+0(((x^2-(5+8)x+(5*8)=0))) so in what base is 5+8 = 12 and 5*8 = 37?
The base must be greater that 8 since one of the solutions is 8.
The base is greater than 10 since 5*8 base 10 is 40 and our product is 37 Try 11. 5+8 base 11 = 12 and (5*8) base 11 = 37.

39. The solution to the quadratic equation x^2 -11x + 22 =0 is x=3 and x=6. What is the base of the numbers? [AU May / June 2012]
                        3+6 = 11                          3*6 = 22
                   3+6 base 8 = 11                3*6 base 8 = 22
So the base is 8

40. Define Prime Implicant.
          Final product term obtained from K-map after combining all possible adjacent squares is known as Prime Implicant.

41 .Realize the function Y=A+B using only NAND gate. [AU Dec 2008]




42. What are Essential Terms? [AU Dec 2009]
          When one Minterm can only be represented by one Prime Implicant then it is called essential term.

43. Convert (1001010.1101001)2 to base 16 and (231.07)8 to base 10. [AU Nov / Dec 2013]
            (4A.B2)16  and (153.109)10.

44. Realize XOR gate using only 4 NAND gates. [AU Nov / Dec 2013]
 


45. State and prove Consensus theorem. (May 2005)[AU May/June 2014]
Consensus theorem:
An expression of the form AB+A’C+BC the term BC is redundant and can be eliminated to form AB+A’C. The theorem used for this simplification is known as consensus theorem.
Proof : AB+A’C+BC = AB+A’C+ (A+A’)BC
= AB+A’C+AB+A’C
= AB+A’C

46. Find the Octal equivalent of hexadecimal number AB.CD [AU Nov/Dec 2010, AU  May/June 2014]
          Hexadecimal to binary         AB16 =  1010 10112
                                                 CD16 = .1100 11012
           Binary to octal         10101011.110011012          = 010 101 011. 110 011 010
                                                = 253.6328

47. Convert (A3B)H into decimal numbers.[AU Nov/Dec 2014]
            A3B16 = (A x 162 + 3 x 161 + B x 160)
                   = (10 x 162 + 3 x 161 + 11 x 160)
                   = (256 + 48 + 11)
                   = (315)10

48. Find the complement of the function F=x'yz'+x'y'z. .[AU Nov/Dec 2014]
F'       =       ( x' y z' + x' y' z )'
                   =       ( x' y z' )' ( x' y' z )'
                   =       ( x + y' + z ) ( x + y + z' )
16 MARKS

1.            Show that Excess-3 code is self-complementing.
2.            Explain how you will construct an (n+1) bit Gray code from an n bit Gray code.
3.            Express the switching function F(A,B)=A in terms of minterms.
4.            Simplify the switching function F(E,D,C,B,A)=å(3,5,6,8,9,12,13,14,19,22,24,25,30).
5.            Apply Demorgans theorem to simplfy (A+BC’)’.
6.            Plot the expression on K-map: F(W,X,Y)= å(0,1,3,5,6)+d(2,4).
7.            Simplify using K-map to obtain a minimum POS expression:
          F=(A’+B’+C+D)(A+B’+C+D)(A+B+C+D’)(A+B+C’+D’)(A’+B+C+D’)(A+B+C’+D)
8.            Reduce the following equation using Quine McCluskey method of minimisation:       
          F(A,B,C,D)= å(0,1,3,4,5,7,10,13,14,15).
9.            State and prove idempotent laws of Boolean algebra.
10.         Using K-map, find the MSP form of F= å(0,4,8,12,3,7,11,15) + d(5).
11.         With the help of a suitable example, explain the meaning of an redundant prime   
          implicant.
12.         Using K-map, find the MSP form of F=å(0-3,12-15) + åd(7,11).
13.         Simplify the following function using K-map:
a.          F(A,B,C,D)= Õ(1,2,4,5,7,8,10,11,13,14).
b.          F(A,B,C,D)= Õ(4,5,6,7,8,12,13) + d(1,15).
14.         Obtain the canonical sum of product form of the function F(A,B,C)=A+BC.
15.         Find the MSP form of F(W,X,Y,Z)= å(1-3,5-10,12-14) using the Quine-McCluskey
          technique.
16.         Simplify the following using the Quine-McCluskey technique
          F(A,B,C,D)=å(0,1,2,3,6,7,8,9,14,15).
17.         Determine the MSP and MPS of F=å(0,2,6-8,10,12,14,15).
18.         Determine the MSP form of the switching function F= å(0,1,4,5,6,11,14,15,16,17,
            20-22,30,32,33,36,37,48,49,52,53,59,63).
19.         Determine the MSP form of F(A,B,C,D)= å(0,2,4,6,8)+ d(10,11,12,13,14,15).
20.         Simplify the following Boolean function by using the Tabulation Method    
          F=å(0,1,2,8,10,11,14,15).
21.         State and prove the postulates of Boolean algebra.
22.         Find the minimum sum of products expression for the following function using Quine-  
          McCluskey method  F(A,B,C,D,E)= å(0,2,3,5,7,9,11,13,14,16,18,24,26,28,30).
23.         Determine the minimum sum of products and minimum product of sums for   
           F=B’C’D+BCD+ACD’+A’B’C+A’BC’D.
24.         Find the minterm expansion of F(A,B,C,D)=A’(B’+D)+ACD’.
25.         State and prove the theorems of Boolean algebra with illustration.
26.         If a manufacture specifies the minimum logical 1(logical 0) at a gate output 4.0V and        
           also specifies that any voltage done upto 3.6V will be considered as logical 1, find the  
          noise margin.
          Formula: Noise Margin = Vlogic 0-Vlogic 1 .Therefore,4.0-3.6=0.4V.
27.         Determine the fanout, given I1H(max)= 40 mA and I0H(max)= 400mA
          Formula: fanout = I0H(max) / I1H(max)= 400mA / 40mA = 10.
28.         Obtain 3-level NOR-NOR implementation of F(A,B,C,D,E,F)= (AB+CD)EF.
29.         Show that if all the gates in a two level OR-AND(AND-OR) gate network are replaced by  
          NOR(NAND) gates, the output function does not change.
30.         Simplify the Boolean function F(A,B,C,D)= å(1,3,7,11,15) +d(0,2,5). If don’t care  
          conditions are not  taken , what is the simplified Boolean function. What are your  
          comments on it? Implement both circuits.
31.         Implement Y=(A+C)(A+D’)(A+B+C’) using NOR gates only.
32.         Write short notes on logic gates.
33.         F3(A,B,C)= å(2,4,5,6), F2(A,B,C)= å(2,3,6,7), F1(A,B,C)= å(2,5,6,7). Implement the   
          above Boolean functions
a.            when each is treated separately and
b.            when sharing common term.
34.         Implement the switching function whose octal designation is 274 using NAND (NOR)    
          gates only.
35.         Show that the NAND operation is not distribute over the AND operation.
36.         Find a network of AND and OR gates to realize F(A,B,C,D)= å(1,5,6,10,13,14).

 


UNIT II

COMBINATIONAL LOGIC

1.  What is a combinational circuit?
          Combinational circuits are used to process binary data. In combinational logical circuits, the output depends on the logical combination of input signals at that instant of time.

2.  Write the steps to obtain the output Boolean functions from a logic diagram?
·            Label all gate outputs that are a function if input variables with arbitrary symbols. Determine the Boolean functions for each gate output.
·            Label the gates that are function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates.
·            Repeat the process outlined in step 2 until the outputs of the circuit are obtained.
·            By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables.

3.  Write the steps to obtain the truth table directly from logic diagram?
·   Determine the number of input variables in the circuit. For n inputs, form the 2n possible input combinations and list the binary numbers from 0 to 2n – 1 in a table.
·   Label the outputs of selected gates with arbitrary symbols.
·   Obtain the truth table for the outputs of those gates that are function of the input variables only.
·   Proceed to obtain the truth table for the outputs of those gates that are function of previously defined values until the columns for all outputs are determined.

4.  Write the design procedure of combinational circuits? [April / May 2011] [AU Dec 2009]
          The procedure involves the following steps:
·   From the specifications of the circuit, determine the required number of inputs and outputs and assign a symbol to each.
·   Derive the truth table that defines the required relationship between inputs and outputs.
·   Obtain the simplified Boolean functions for each output as a function of the input variables.
·   Draw the logic diagram and verify the correctness of the design.

5.  What are full adders?
          Full adder is a combinational logic circuit which performs addition of 3 bits ie.two input bits and a carry input from the previous stage.

6.  Write the different numeric and alphanumeric binary codes of a digital system.
Numeric binary codes:
1.            8421- BCD
2.            Excess-3 code
3.            Gray code

Alphanumeric binary codes:
1.            ASCII – American Standard Code for Information Interchange.
2.            EBCDIC – Extended Binary-Coded Decimal Interchange Code.

7. Write the simplified expression for the full adder circuit. [AU Dec 2009]
          S = x1 y1z + x1 yz1 + x y1z1 + xyz
          C = xy + xz + yz
         
8. What is a Magnitude Comparator? [AU Dec 2009]
          A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes.

9. What is mean by HDL?
                              A Hardware Description Language (HDL) is a language that describes the hardware of digital systems in a textual form, which resembles a programming language and used as a documentation language also.

10.   What is logic simulation? [AU May / June 2012]
          Logic simulation is the representation of the structure and behavior of a digital logic system through the use of computer. A simulator interprets the HDL description and produces readable output such as timing diagram, that predicts how the hardware will behave before it actually fabricated.

11.         What is meant by system primitive?
          The logic gates used in HDL descriptions with keywords and, or, etc., are defined by the system and are referred to system primitives.

12.         What is meant by user-defined primitives?
          The user can create additional primitives by defining them in a tabular form.

13. What is logic synthesis? [AU May / June 2012]
          Logic synthesis is the process of deriving a list of components and their interconnections from the model of a digital system described in Hardware description language. It is based on formal exact procedures that implement digital circuits and consists of that part of a digital design that can be automated with computer software.

14. What is half adder? [AU Nov/Dec 2014]
                    It is combinational circuit that performs the addition of two bits.
          The simplified expression for half adder is:
                             S= x’y+xy’
                             C=xy

15. What is binary adder?
          It is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry of the next full adder in the chain.

16. What is Propagation Delay?
          The delay produced in the the combunational circuits when the signal propagates through the gates before the correct output sum is available in the output terminals.

17. What is Carry generate and Carry propagate?
he expression for a circuit is
                             Pi = Ai      Bi
                             Gi = AiBi
The output sum and carry can be expressed as
                            Si = Pi        Ci
Here Gi called a Carry Generate and it produces a carry of 1 when both Ai and Bi are 1regardless of the input carry Ci.
Pi is called the Carry Propagate, the term associated with the propagation of the carry from Ci to C i+1.

18. What is gate delay?
          When HDL is used during simulation, it is necessary to specify the amount of delay from the input to the output of gates. In verilog, the delay is specified in terms of time units and the symbol #.

19. What is System primitives?
          The logic gates used in HDL descriptions with keyword and, or, etc are defined by the system and are referred to as system primitives.

20. What is user defined primitives?
          The user can create additional primitives by defining them in a tabular form. These types of circuits are referred to as user defined primitives.

21. What is over flow?
          Over flow is problem in digital computers because the number of bits that hold the number is   finite and a result that contains n+ 1 bit cannot be accommodated. For this reason many computers detect the occurrence of an over flow and when occurs a corresponding of flip flop is set that can be checked by the user. An overflow condition can be detected by observing the carry into sign bit position and the carry out of the sign bit position. If these two caries are not equal, an overflow has occurred.

22. Implement a full adder with two half adders. [AU Nov / Dec 2012] [AU Dec. 2008]

23. Implement a 4-bit even parity checker. [AU Nov / Dec 2012]


     24. What are the applications of HDL processing? [AU Dec. 2008]
Ø     Logic Simulation
Ø     Logic Synthesis

25. Distinguish between sequential and combinational logic circuits. [AU April / May 2011]

S.No.
Combinational Circuit
Sequential Circuit
1.
It contains no memory elements
It contains memory elements
2.
The present value of it’s outputs are determined solely by the present values of it’s inputs
The present value of it’s outputs are determined by the present value of it’s inputs and it’s past state
3.
It’s behavior is described by the set of output functions
It’s behavior is described by the set of next-state(memory) functions and the set of output functions


26. Write the names of Universal gates.
1. NAND gate
2. NOR gate               

27. Why are NAND and NOR gates known as universal gates?
          The NAND and NOR gates are known as universal gates, since any logic function can be implemented using NAND or NOR gates.


28.         What is decoder?
          A decoder is a combinational logic device which has ‘n’ input lines and 2n output lines, which activates a particular output line based on the combination of input.
         
29.         What is encoder?
          An encoder is a combinational logic device that takes decimal or octal digit as its input and gives coded output such as binary or BCD. It functions reverse to that of a decoder.

 30.  What is Multiplexer?
           Multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. A multiplexer is also called a data selector.

31.  What is Demultiplexer?
           Demultiplexer is a circuit that receives information from a single line and directs it to one of 2n possible output lines. A decoder with an enable input is referred to as a demultiplexer.

32. What is a Priority encoder? AU Nov / Dec 2010]
          Priority encoder is a encoder that produces a BCD output corresponding to the highest order decimal digit appearing at the input.

31. Construct a 4x16 decoder using 3x8 decoders. [AU Nov Dec 2012]


32. Define Tri-State gates. [AU May / June 2012]
          A Multiplexer can be constructed with three state gates. It contains 3 states. 2 states are signals equivalent to logic 1 and 0. 3rd state is a high impedance state. High impedance state behaves like an open circuit which means that the output appears to be disconnected and the circuit has no logic significance.

33. Write the stimulus for 2-to-1 line multiplexer. [AU May / June 2012]
                        module text_mux2;
reg i0,i1;
reg s0;
wire out;
mux2 mymux(out,i0,i1,s0);
initial
$monitor($time,"s0=%b,i0=%b,i1=%b,out=%b\n",s0,i0,i1,out);
initial
begin
s0=0;i0=0;i1=0;
#50 s0=0;i0=0;i1=1;
#50 s0=1;i0=0;i1=1;
#50 s0=0;i0=1;i1=0;
#50 s0=1;i0=1;i1=0;
end
endmodule

34. Mention any two applications of multiplexers. [AU April / May  2011][ AU Nov/Dec 2014]
            Applications are cell phone systems, instrumentation, and any other function where only one transmission channel (e.g a radio transmitter) is available.

 35. Realize the half adder using equal number of OR and AND gates. [AU April / May 2011] [AU Nov / Dec 2010]




36. Differentiate multiplexer and demultiplexer. [AU Dec 2009]
                        A multiplexer is a combinational circuit that selects binary information from one of many input line and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Multiplexer is otherwise called as Data Selector.
                   A demultiplexer is a circuit that receives information from a single line and directs it to one of 2n possible output line. A decoder with an enable input can function as a Demultiplexer.
                                   
37. What are the two steps in Gray to binary conversion?
          The MSB of the binary number is the same as the MSB of the gray code number. So write it down. To obtain the next binary digit, perform an exclusive OR operation between the bit just written down and the next gray code bit. Write down the result.

38. Convert gray code 101011 into its binary equivalent.
          Gray Code : 1 0 1 0 1 1
          Binary Code 1 1 0 0 1 0

39. Convert 10111011 is binary into its equivalent gray code.
          Binary Code: 1 0 1 1 1 0 1 0 1 1
          Gray code: 1 1 1 0 0 1 1 0
          1 0 1 0
          0 0 1 1
          1 1 0 1
40. Draw a 4-bit binary to gray code converter circuit. [AU Nov /  
       Dec 2010]


41.What is mean by module?
          The module is the basic building block of Verilog HDL.

42.What are the different modeling techniques to describe a module? [AU Nov / Dec 2011]
1.    Gate-level modeling using instantiation of primitive gates and user-defined modules.
2.    Dataflow modeling using continuous assignment statements with keyword assign.
3.    Behavioral modeling using procedural assignment statements with keyword always.

43. What are the system tasks that are useful for display?
$display
$write
$monitor
$time
$finish

44.Obtain the truth table for BCD to Excess-3 code converter. [AU Nov / Dec 2013]

TRUTH TABLE
Input (BCD)
Output (Excess-3)
A
B
C
D
W
X
Y
Z
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0

45.Draw the truth table and circuit diagram of 4 to 2 encoder. [AU Nov / Dec 2013]


46.Draw the  circuit for 2-to-1 line multiplexer [AU May/June 2014]



47. Distinguish between decoder and demultiplexer. (May,04;Nov,09) [AU Nov/Dec 2014]

S.No
Decoder
Demultiplexer
1
Decoder is a many input to many
Output device
Demultiplexer is a one input to many
output devices.
2
There are no selection lines
The selection of specific output line is
Controlled by the value of selection line


16 MARKS

1.            Explain the analysis and design procedure for combinational circuits.
2.            Design half-adder using only NAND gates.
3.            Design full-adder using only NOR gates.
4.            Explain the method used for fast addition(carry lookahead generation).Pg.No:124-126.
5.            Design the 4-bit BCD adder using 4-bit binary adders.Pg.No:129-131.
6.            Design a combinational logic circuit whose outputs are F1=A’BC+AB’C and     
          F2=A’+B’C+BC’.
7.            Distinguish between Boolean addition and Binary addition.
8.            Using a single 7483, draw the logic diagram of a 4 bit adder/subtractor.
9.            Draw a diode ROM which translates from BCD 8421 to excess-3 code.
10.         Realize a BCD tp Excess-3 code conversion circuit starting from its truth table.
11.         Design a combinational circuit which accepts 3 bit binary number and converts its
          equivalent Excess-3 code.
12.         Derive the simplest possible expression for driving segments ‘a’ through ‘g’ in an 8421 B
CD to seven- segment decoder for decimal digits 0 through 9. Output should be active high. Design the combinational  circuit for this.
13.         Draw the circuit for 3-to-8 decoder and explain.Pg.No:134-136.
14.         Implement the following Boolean function using 8-to-1 & 4-to-1 Multiplexer F(A,B,C)=
          å(1,3,5,6).
15.         Implement the following Boolean function using 4-to-1 MUX F(A,B,C,D)=
å(0,1,2,4,6,9,12,14).[The function has 4 variables. To implement this function we require 8-to-1 Mux ie., two 4-to-1 Mux].
16.         Implement the following Boolean function using 8-to-1 Multiplexer   
            F(A,B,C,D)=A’BD’+ACD+B’CD+A’C’D
17.         Implement the following Boolean function using 8-to-1 Multiplexer  
18.         F(A,B,C,D)=Õ(0,3,5,8,9,10,12,14).
19.         Implement the following Boolean function using 8-to-1 Mux    
          F(A,B,C,D)=å(0,2,6,10,11,12,13) +  d(3,8,14).
20.         Design 1-to-8 demultiplexer using two 1-to-4 demultiplexers.
21.         Implement full subtractor using demultiplexer.
22.         State the condition for B=I2 in the Boolean expression B=I0S0’S1’ + I1S0’S1 + I2S0S1’ +
I3S0S1. What is  the combinational logic circuit realised by the above Boolean expression?
           Sol: To satisfy the condition B=I2 , I2S0S1’ = I2 
        \S0S1’=1.\ S0 =1 and    S1=0. The combinational logic circuit realised by the above  Boolean expression is 4-to-1 Mux with I0, I1, I2 and I3 are the four inputs, B is the output, and S0  and S1 are the selection lines.
23.         Realize F(W,X,Y,Z) = å(1,4,6,7,8,9,10,11,15) using 4-to-1 MUX.
24.         Write the HDL gate-level and dataflow description of the following circuits
          a. Binary to BCD converter            b. BCD to Binary converter
          c. BCD to Excess-3 code converter d. Excess-3 to BCD code converter
          e. Binary to Gray code converter    f. Gray to Binary code converter
          g. BCD to Gray code converter.
25.         Implement the switching function F=å(0,1,3,4,7) using a 4 input MUX.
26.         Explain how you will build a 24 bit magnitude comparator using 7485.
27.         State the advantages of complex MSI devices over SSI gates.
28.         Implement the switching function F(A,B,C)= å(1,2,4,5) using the DEMUX.
29.         Implement the switching function F= å(0,1,3,4,12,14,15) using an 8 input MUX.
30.         Implement the switching function F= å(1,2,4,5) using the dual two line to 4 line  
          decoder/demultiplexer.



UNIT III

 SYNCHRONOUS SEQUENTIAL LOGIC

   

1. How a sequential circuit differs from a combinational circuit?

          Sequential circuits are also same as combinational circuits except that the storage elements are connected to form the feedback path.

2. What is a latch?
          It is used for maintaining a binary state until directed by an input signal to switch states and it differs by
                   (i) Number of inputs and
                   (ii)The manner in which input affects.

3.  What is a flip-flop?
          Flip-flop is a logic device capable of storing single bit of information.

4. Draw the characteristic table for JK flip-flop. [AU May / June 2012]

J
K
Q(t+1)
Q(t)
0
0
Q(t)
No change
0
1
0
Reset
1
0
1
Set
1
1
Q(t)
Complement
                  
                   
         
5. What are state tables and state diagrams?
          The time sequence of inputs, outputs and flip-flop states are enumerated in state table which gives the Next sate as a function of present state and inputs.
          The pictorial view of state transitions delivered from given logic diagram is called as the state diagram.


6. Give the characteristic table for D and T flip flop?
                  
T
Q(t+1)
Q(t)
0
0
No change
1
1
Complement

D
Q(t+1)
Q(t)
0
0
Reset
1
1
Set

         

                            

7. What is state reduction?
          The reduction in the number of flip-flops in a sequential circuit is referred as the state reduction. The reduction algorithms are concerned with procedures for reducing the number of states in the state table. While keeping the external inputs, outputs unchanged.

8. What is called state assignment? What are the 3 possible binary state assignments?
                   It is concerned with assigning values with the   various possible states in order to design sequential circuits with physical components. The three possible state assignments are:
(i)                           Binary assignment.
(ii)                          Gray code
(iii)                         One-hot

9. What are the steps to design synchronous sequential circuits?[ AU Nov/Dec 2014]
1.            From the description derive the state diagram.
2.            Reduce the number f states if necessary.
3.            Assign binary values to the states.
4.            Obtain the binary-coded state table.
5.            Choose the type of flip-flops.
6.            Derive simplified input-output equations.
7.            Draw the logic diagram.

10. What is an excitation table?
          Excitation table lists the required inputs of the flip-flops for a given change of state during the design process of a given logic.

11. Give the difference between synchronous and asynchronous sequential circuits?
[ AU Nov/Dec 2014]
         

S.No

Synchronous sequential circuits
Asynchronous sequential circuits

1
Memory elements are clocked flipflops

 
Memory elements are either unclocked
flip-flops or time delay elements.

2
The change in input signals can
Affect memory element upon activation
The change in input signals can affect
Memory element at any instant of time.

 

3
The maximum operating speed of
Clock depends on time

delays involved.
Because of the absence of clock,it can
operate faster than synchronous circuits.

 

4

Easier to design

More difficult to design


12. What is a   register?
          A register is a group of flip-flops and gates that effect their transition. The flip-flop hold the binary information   and the gates determine how the information is transferred into the register.
         
13. What are the capabilities of shift register?
(i)     A clear   control to clear the register to 0.
(ii)    A clock input to synchronize the operations.
(iii)   A shift right control and a shift right control
(iv)   A parallel load   control
(v)    N parallel output. Lines.
(vi)   A control state

 14. List few applications of Shift register? [AU May / June 2012,2014]
§  Time delay
§  Ring counter
§  Serial to parallel data converter
§  Keyboard encoder

15. What are two types of counters? Explain Shortly.
            Ripple counter:
                   In this, flip-flop output transition   serves as a   source for triggering other flip-flops.  All flip-flops are not triggered by common clock.
            Synchronous counter
                   All flip-flops are triggered by common clock.         

16. Explain serial transfer with two shift registers.
                             It is assumed that two shift registers have four bits each. Then the serial transfer is given as,
                   Timing pulse            Shift register A                  Shift register B
                   Initial value              1  0  1  1                          0  0  1  0
                   T1                          1  1  0  1                          1  0  0  1
                   T2                          1  1  1  0                          1  1   0  0
                   T3                          0  1  1  1                          0  1  1  0
                   T4                          1  0   1 1                          1  0  1  1

17. What are two types of ripple counter?
            Binary ripple counter:
          It consists of a series connection of complementing flip-flops with output of each flip-flop connected to the input of next higher order flip-flop.
            BCD ripple counter:
          It follows a sequence of ten states and returns to zero after 9.It contains 4 flip-flops to represent each decimal digit.

18. Give the various synchronous counters.
  • Binary counter [AU Nov / Dec 2010]
                   Complementing flip-flops and AND gates are used.
  • Up-Down counter
                   Two inputs are used to mention the type of counter (up/down)
                                      Up      Down            Type of Counter
                                      0        0                  no change in previous input.
                                      0        1                  down counter
                                      1        0                  Up counter
                                      1        1                  up counter
  • BCD Counter
                   Binary coded decimal counts from 0000 and come back to 0000 while 1001 comes.

19. Write the behavioral description for 4-bit shift register.
                        Module   shiftreg(s1,s0,CLK)
                                    Input s1,CLK;
                                    Output s0;
                                    Reg [3:0] Q;
                                    Assign   s0= Q[0];
                                    Always  @ (posedge CLK)  
                                      Q={s1,Q[3:1]};
                        Endmodule

20. What is a ring counter? [AU Nov / Dec 2012]
          A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others all cleared.

21. What are the classifications of sequential circuits?
The sequential circuits are classified on the basis of timing of their signals into two types.
  • Synchronous sequential circuit.
  • Asynchronous sequential circuit.
22. What is the operation of D - flip flop?
          In D flip flop during the occurrence of clock pulse if D=1, the output  is set and if D=0, the output is reset.

23. Write the Characteristic equation of JK flip flop. [AU May/ June 2012]
          Characteristic equation Q(next) = JQ' + K'Q

24. Signify the switch-tail ring counter. [AU April / May 2011]
          Switch-tail ring counter is a circular shift register with the complement output of the last flip flop connected to the input of the first flip flop.
         
25. Distinguish between Latches and Flip –flops. [AU April / May 2011]
          Flip-Flop and Latch are the two basic building blocks of a sequential circuit. But there is a subtle difference between the two.
          A flip-flop continuously checks its inputs and correspondingly changes its output only at times determined by clocking signal. Where as a latch is a device which continuously checks all its input and correspondingly changes its output, independent of the time determined by clocking signal.
          A unique signal called "enable" is provided with latch. The output changes only when the enable signal is active. No change in output takes place when the enable signal is inactive.

26. What are mealy and Moore machines? [AU Dec. 2009]
          In Mealy model, the output is a function of both the present state and input.
          In Moore model, the output is a function of the present state only.

27. Difference between Synchronous Counter and Asynchronous Counter
  • Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops
  • Synchronous counter – all state bits change under control of a single clock
(or)
SNO
SYNCHRONOUS COUNTERS
ASYNCHRONOUS COUNTERS
1
In this counter, common clock input is connected to all the flip flops. Thus they are clocked simultaneously.
In this counter, first flip flop is clocked by the external clock pulse and then each successive flip flop is clocked by the output of previous flip flop.
2
Propagation delay is equal to the delay of single flip flop.
Propagation delay is the cumulative sum of Propagation delay of all flip flops.
3
Also called parallel counters
Also called ripple or serial counters

28. What is a flip flop? Give its types. [AU Nov / Dec 2010]
          Flip - flop is a sequential device that normally samples its inputs and changes its outputs only at times determined by clocking signal. Its types are:
1] S.R. latch
2] D latch
3] Clocked J.K. flip-flop
4] T flip-flop

29. What are the types of triggering a flip flop?
          The types of triggering a flip flop are,
  • Level triggering
  • Edge triggering.

30. What is edge triggering in flip flops? [AU Dec 2009]
          Edge triggering means that the flip flop changes state either at the positive edge(rising edge) or at the negative edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock.

31. What is meant by level triggering?
          In level triggering the output of the flip-flop changes state or responds only when the clock pulse is present.
32. Give the excitation table of JK flipflop. [AU Dec 2009]
            Excitation Table for a JK Flip Flop ("X" is "don't care")
Previous State -> Present State
J
K
0 -> 0
0
X
0 -> 1
1
X
1 -> 0
X
1
1 -> 1
X
0

33. What is meant by the term State Reduction? [AU Nov / Dec 2010]
(or) What is the need of state reduction? [AU Nov/Dec 2009]
            The reduction of the number of flip-flops in a sequential circuit is referred to as the state reduction problem. State-reduction algorithms are concerned with procedures for reducing the number of states in a state table, while keeping the external input-output requirements unchanged. Since (N) flip-flops produce (2N) states, a reduction in the number of states may (or may not) result in a reduction in the number of flip-flops.

34. Write down the characteristics equation of S-R flipflop. [AU Nov/Dec 2014]
("X" is "don't care")
Previous
state
Present
state
S
R
0
0
0
X
0
1
1
0
1
0
0
1
1
1
X
0
Characteristic equation Q(next) = S + QR′

16 MARKS

1.            Draw the state diagram and characteristic equation of T, D and JK Flip Flops.
2.            Draw the schematic diagram of Master slave JK FF and input & output waveforms.
          Discuss how does it prevent race around condition.
3.            Explain the operation of JK and clocked JK flip-flops with suitable diagrams.
4.            Design and explain the working of synchronous mod-3 counter.
5.            Design and explain the working of mod-7 counter.
6.            Draw and explain the working of 4-bit Up-Down synchronous counter.Pg.No:234-235.
7.            Using SR (JK) flip-flops, design a parallel counter which counts in the sequence 000,
          111, 101, 110, 001, 010, 000.
8.            Using JK flip-flops, design a synchronous sequential circuit having one input and one
output. The output of the circuit is a 1 whenever three consecutive 1’s are observed. Otherwise the output is zero. Design a synchronous binary counter using T flip-flops.



UNIT IV

 ASYNCHRONOUS SEQUENTIAL LOGIC

1. What is hamming code?
          It is the code used for single bit error detection and correction. In this code k parity bits are added to n-bit data word, forming n + k bits. The positions numbered as power of 2  are reserved    for parity bits The parity assigned at source are checked at receiver side to detect the errors.
          Ex:     1        2        3          4      5       6       7       8       9       10     11     12 
                   P1       P2      1        P4      0        1        1        P8      0        1        0        1

2. What is a flow table? [AU Dec 2009] How it differs from state table?
          A flow table contains the states represented by letters or symbols where as in the state tables the internal states are assigned binary numbers. The flow table also includes the output values of the circuit for each stable state.
 
3. What is the procedure for obtaining transition table in asynchronous sequential circuits?
  • Determine all feedback loops in the circuit.
  • Designate the number of outputs (Yi) for each feedback loop with the corresponding external inputs.
  • Derive Boolean function for all outputs.
  • Plot each function in map using Yi and external inputs.
  • Combine all the tables into one table.
  • Circle the values Y in each square that are equal to value 0f Y=Y1,Y2,……Yk in the same row.

4. What are race conditions? [ AU Nov/Dec 2009, 2014] [AU May / June 2012,2014]
          A race condition is said to exist in an asynchronous sequential circuit when two are more binary state variables change value in response to a change in an input variable.
*If the number of output states depends on the order in which state variable change, it is a critical state.
*If the final stable state that the circuit reaches does not depend upon order in which the state variable changes, it is a non-critical race.

5. Write steps followed in the design procedure.
  • Obtain primitive flow table from given specifications.
  • Reduce the flow table by merging rows.
  • Assign binary state variables to each row.
  • Assign the output values to get output maps.
  • Simplify the Boolean function of Excitation and output variables and draw logic diagram.

6. What is an implication table? [AU Nov / Dec 2011]
          It is a chart that consists of squares, one for every possible pair of states that provide spaces for a listing any possible implied state.

7. What are compatible pairs and maximal compatibilities? [AU April / May 2011]
          Two states are compatible if in every column of the corresponding rows in the flow table, are identical or compatible and if here is no conflict in the output values. The maximal compatibility is the group of compatibles that contains all possible combinations of compatible states.

8. What is a close covering condition?   
          *        It is the condition for row merging of chosen compatibles of an implication table of a given asynchronous circuit that cover all states and must be closed.
          *        The closure condition is satisfied if there are no implied states or if the implied states, is called a close covering.

9. An asynchronous sequential circuit is given as excitation and output functions. Describe in words the behavior of circuit.
                             Y=x1x2+( x1+ x’2)y
                             Z=y
          When the input is 01, output is 0
          When the input is 10, output is 1.
Whenever the input assumes one of the other two combinations, the output retains its previous value.

10. Why Race-Free state assignment is important?
          In design of asynchronous sequential circuits the proper binary values are assigned to convert flow table into its equivalent   transition table. Here the race free assignment ensures that the critical races are prevented which is given by one of the following methods.
  • Shared-row method
  • Multiple row method.

11. What is meant by secondary and excitation variables?
          The present state variable in asynchronous sequential circuits is called secondary variable.
          The next state variable in asynchronous sequential circuits is called excitation variable.

12.   Define Primitive Flow Table. [AU Nov/ Dec 2010]
                                          It is a special case of flow table. It is defined as a flow table which has exactly one stable state for each row in the table.

13.   What is meant by Hazards? [AU April / May 2011]
                             The unwanted switching transients that may appear at the output of a circuit are called Hazards.

14.   What are the three types of hazards? [AU Nov / Dec 2011][AU May/Jun 2014]
  • Static-1 hazard
  • Static-0 hazard
  • Dynamic hazard

15.   Define Static-1 hazard.
      In a combinational circuit, if output goes momentarily 0 when it should remain a 1, the hazard is known as static-1 hazard.

16.   Define Static-0 hazard.
      If the output goes momentarily 1 when it should remain a 0, the hazard is known as static-0 hazard.

17.   Define Dynamic hazard.
      It is another type of hazard in which output changes three or more times when it should change from 1 to 0 of from 0 to 1.

18.   What is essential hazard? [AU May / June 2012]
          It is caused by unequal delays along two or more paths that originate from the same input. Such hazards can be eliminated by adjusting the amount of delays in the affected path.

19.   What is meant by merging?
The grouping of stable states from separate rows into one common row is called merging.

20.   What is meant by debounce circuit?
A debounce circuit is one that removes the series of pulses that result from a contact bounce and produces a single smooth transition of the binary signal from 0 to 1 or from 1 to 0.

21.   Distinguish between a conventional flow chart and an ASM chart. [AU Nov/ Dec 2012]
A Special Flowchart developed to design Digital hardware algorithms is called Algorithmic State Machines (ASM). A conventional flowchart describes sequence of Procedural steps without concern for their time relationship.
         
22. Draw the block diagram of an asynchronous sequential circuit. [AU Nov/ Dec 2012]

23.   List the elements in the ASM chart. [April / May 2011]
          An ASM chart consists of an interconnection of four types of basic elements: state names, states, condition checks and conditional outputs.

24.   Construct JK flipflop using D flipflops? [AU Dec 2008] [AU Nov / Dec 2013]

           


25. What are the two types of Asynchronous sequential circuits? Or Distinguish fundamental mode circuit and pulse mode circuit. [ AU Nov / Dec 2013]
  • Fundamental mode
  • Pulse mode
Fundamental mode: [AU Dec 2009]
            The input variables change only when the circuit is stable. Only one input variable can change at a given time. Inputs are levels and not pulses.
Eg: Ordinary Asynchronous Sequential Circuit
Pulse Mode:
            Input variables are pulses instead of levels. The width of the pulses is long enough for the circuit to respond to the input. The pulse width must not be so long.
                   Eg: Asynchronous Sequential circuits with latches.

26.Write the HDL code for up-down counter using behavioral model. [AU Nov / Dec 2013]
module behav_counter( d, clk, clear, load, up_down, qd);

// Port Declaration

input   [7:0] d;
input   clk;
input   clear;
input   load;
input   up_down;
output  [7:0] qd;

reg     [7:0] cnt;

assign qd = cnt;

always @ (posedge clk)
begin
    if (!clear)
        cnt = 8'h00;
    else if (load)
        cnt = d;
    else if (up_down)
        cnt = cnt + 1;
    else
        cnt = cnt - 1;
end

endmodule
16 MARKS

1.             An asynchronous sequential machine operating in fundamental mode has two input lines
x1 and x2 and one output z. The output is zero whenever x2 is 0 with the first change in x1 occurring while x2 is 1, z becomes a ‘1’ and remains ‘1’ until x2 returns to zero. Write down a state table for this machine.
2.             A pulse mode asynchronous machine has two inputs. It produces an output whenever
two consecutive pulses occur on one input line only. The output remains at 1 until a pulse has occurred on the other input line. Draw the state table for the machine.
3.             How will you minimize the number of rows in the primitive state table of an incompletely
          specified sequential machine?
4.             Construct the state diagram and primitive flow table for an asynchronous network that
has two inputs and one output. The input sequence x1x2 = 00, 01, and 11 causes the output to become 1. The next input change then causes the output to return to 0. No other inputs will produce a 1 output.
5.             How can essential hazards and static hazards eliminated?
6.             Implement the switching function F= ∑ (1,3,5,7,8,9,14,15) by a static hazard free two
          level AND-OR  gate network.
7.             Implement the switching function F= ∑ (0,1,3,4,8-12) by a static hazard free two level
          OR-AND gate network.
8.             Show that dynamic hazards do not occur in two level AND-OR gate networks.
9.             Find a static and dynamic hazard free realization for the following function using
a.          NAND gates
b.          NOR gates     F(A,B,C,D)= ∑(1,5,7,14,15).



UNIT V

MEMORY AND PROGRAMMABLE LOGIC

 1.  What are the type of memories?
  • Random access memory(RAM)
                             Static RAM
                             Dynamic RAM
  • Read-Only Memory
                             EPROM
                             EEPROM

 2. What are the difference between a static RAM and the Dynamic RAM?
  • Static RAM have bipolar or MOSFET latches as storage cells that can retain data indefinitely.
  • Dynamic RAM have capacitive storage cells that must be refreshed periodically.

 3. Advantages of dynamic RAM over static RAM?
            Memory arrays can be constructed on a chip at a lower cost than in static memory.

 4. What is a PAL?
          PAL is programmable array logic. PAL is a programmable logic device similar to programmable logic array. The PLA has an array on AND gate & OR gate, in which the OR gate array can be programmed to obtain a variety of necessary logic functions. In PAL, the AND gate array is programmed to generate any required product of the input variables.

 5.What is PLD? [AU Nov / Dec 2012]
            A combinational PLD (Programmable Logic Device) is an integrated circuit with programmable gates divided into AND array and an OR array to provide an AND-OR sum of product implementation.

6.  What is Word and Byte?
            A memory unit stores binary information in groups of bits called words.
          A group of eight bits is called bytes.

7.  What is access time of a memory?
            It is the time required to select a word and read it.

8.  What is Hamming code?
            It is an error correcting code. In this K parity bits are added to an n-bit data word, forming a new word of n+k bits.

9.  What is ROM?
            It is a memory device in which permanent binary information is stored. It consists of K inputs and n outputs. The input provides the address for the memory and the output s give the data bits of the stored word which selected by the address.

10. What are the three types of Combinational PLDs?
·                     Programmable read-only memory(PROM)
·                     Programmable array logic(PAL)
·                     Programmable logic array(PLA)

11. Write the construction of PROM?
            The PROM has a fixed AND array constructed as a decoder and programmable OR array. The programmable OR gates implement the Boolean function in sum of minterms.

12. What is macrocell?
            Each section of SPLD is called macrocell. It is a circuit that contains a sum-of- products combinational logic function and an optional flip-flop.

13. What is programmable logic array? How it differs from ROM?
          In some cases the number of don`t care conductions is excessive, it is more economical to use a second type of LSI component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the variables and does not generates all the minterms as in the ROM.

14. Explain PROM.
          PROM (Programmable Read Only Memory); It allows user to store data or program. PROMs use the fuses with material like Nichrome and polycrystalline. The user can blow these fuses by passing around 20 to 50mA of current for the period 5 to 20μs. The blowing of fuses is called programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored permanent.

15. Explain EPROM.
          EPROM (Erasable Programmable Read Only Memory) uses MOS circuitry. They store 1`s and 0`s as a packet of charge in a buried layer of the IC chip. We can erase the stored data in the EPROM’s by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is not possible to erase selective information. The chip can be reprogrammed.

16. Explain EEPROM.
          EEPROM (Electrically Erasable Programmable Read Only Memory) is also uses MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since the information can be changed by using electrical signals.
         
17. What is RAM?
          It is expended as Random Access Memory. It is a memory device which is used to store the data until the power is switched off. Read and write operations can be carried out.

18. Mention some applications of EEPROM?
          The EEPROM is used to store data permanently and can be quickly erasad. This property of the EEPROM makes it useful in
a.            microcontrollers
b.            USB storage devices
c.            Home appliances
d.            Calculators and digital diaries


19. What is the primary difference between PLA and PAL? [AU Nov / Dec 2011]

PLA
PAL
In PLA both the AND & OR array are programmable.
In PAL only the AND array is programmable
In PLA only combinational circuits are designed
In PAL both combinational and sequential devices can be programmed due to the presence of flip flops.


20.  What is field programmable logic array?
          The second type of PLA is called a field programmable logic array. The user by means of certain recommended procedures can program the EPLA.

21. Give the comparison between PROM and PLA.

PROM
PLA
And array is fixed OR array is Programmable.
Both AND & OR arrays are array is programmable.
Cheaper and simple to use.
Costliest and complex than PROMS.


22. Give the comparison between SRAM and DRAM.
SRAM
DRAM
It uses 6 transistors in its circuit
It uses 3 or 1 transistors in its circuit.
It doesn’t use a capacitor.
It uses a capacitor for bit storage.
Refresh is not needed
Refresh is needed for capacitor or capacitor should be charged frequently.








 
23.Distinguish EEPROM and flash memory. [AU Nov / Dec 2013]
In EEPROMs:
·                     The chip does not have to removed to be rewritten.
·                     The entire chip does not have to be completely erased to change a specific portion of it.
·                     Changing the contents does not require additional dedicated equipment.
          Instead of using UV light, you can return the electrons in the cells of an EEPROM to normal with the localized application of an electric field to each cell. This erases the targeted cells of the EEPROM, which can then be rewritten. EEPROMs are changed 1 byte at a time, which makes them versatile but slow. In fact, EEPROM chips are too slow to use in many products that make quick changes to the data stored on the chip.
          Manufacturers responded to this limitation with Flash memory, a type of EEPROM that uses in-circuit wiring to erase by applying an electrical field to the entire chip or to predetermined sections of the chip called blocks. Flash memory works much faster than traditional EEPROMs because it writes data in chunks, usually 512 bytes in size, instead of 1 byte at a time.
24.Define ASIC. [AU May/Jun 2014]
          An ASIC (application-specific integrated circuit) is a microchip designed for a special application, such as a particular kind of transmission protocol or a hand-held computer. You might contrast it with general integrated circuits, such as the microprocessor and the random access memory chips in your PC. ASICs are used in a wide-range of applications, including auto emission control, environmental monitoring, and personal digital assistants (PDAs).



25.What is Memory Decoding? [AU May/June 2014]
  • The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip.
·         In order to splice a memory device into the address space of the processor, decoding is necessary.  For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space.
·         However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.
·         A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space.


16 MARKS

1.            Implement the following Boolean expressions using PROM
               F1(A,B,C)= å(0,2,4,7), F2(A,B,C)= å(1,3,5,7).
2.            Implement the following Boolean function using PLA F1(A,B,C)= å(0,1,3,5), F2(A,B,C)=
          å(0,3,5,7).
3.            Implement the switching functions Z1=AB’D’E + A’B’C’D’E’ + BC + DE ,
           Z2= A’C’E, Z3=BC+DE+C’D’E’+BD, Z4=A’C’E+CE using a 5x8x4 PLA.
4.            Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using
          ROM array.
5.            Design a combinational circuit using a ROM, that accepts a 3-bit number and generates
          an output binary number equal to the square of the given input number.
6.            Implement the following Boolean functions using PAL
               w(A,B,C,D)= å(0,2,6,7,8,9,12,13),
               x(A,B,C,D)= å(0,2,6,7,8,9,12,13,14),
               y(A,B,C,D)= å(2,3,8,9,10,12,13), z(A,B,C,D)= å(1,3,4,6,9,12,14).
7.            Implement the following Boolean functions using PAL
          A(x,y,z)= å(1,2,4,6), B(x,y,z)= å(0,1,6,7), C(x,y,z)= å(2,6),
          D(x,y,z)= å(1,2,3,5,7).

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